Alif Semiconductor /AE512F80F5582LS_CM55_HP_View /SDMMC /SDMMC_HOST_CTRL2_R

UHS Mode or eMMC Speed Mode Select. These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC speed mode. UHS mode (SD mode only):

0 (Val_0x0): SDR12

1 (Val_0x1): SDR25

2 (Val_0x2): SDR50

1.8 V Signaling Enable. This bit controls voltage regulator for I/O cell in UHS-I or eMMC speed modes. Setting this bit from 0x0 to 0x1 starts changing the signal voltage from 3.3 V to 1.8 V. The Host Controller clears this bit if switching to 1.8 signaling fails. Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50).

0 (Val_0x0): 3.3 V signalling

1 (Val_0x1): 1.8 V signalling

Driver Strength Select. This bit is used to select the Host Controller output driver in 1.8 V signaling UHS-I or eMMC speed modes. The bit depends on setting of the PRESET_VAL_ENABLE bit.

0 (Val_0x0): Driver TYPEB is selected

1 (Val_0x1): Driver TYPEA is selected

2 (Val_0x2): Driver TYPEC is selected

3 (Val_0x3): Driver TYPED is selected

ADMA2 Length Mode. This bit selects ADMA2 Length mode to be either 16-bit or 26-bit.

0 (Val_0x0): 16-bit Data Length mode

1 (Val_0x1): 26-bit Data Length mode

CMD23 Enable. If the card supports CMD23, this bit is set to 0x1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer.

0 (Val_0x0): Auto CMD23 is disabled

1 (Val_0x1): Auto CMD23 is enabled

Host Version 4 Enable. This bit selects either Version 3.00 compatible mode or Version 4 mode. Functions of following fields are modified for Host Version 4 mode:

• SDMA Address: SDMA uses the SDMMC_ADMA_SA_LOW_R register (0x58 - 0x5F) instead of the SDMMC_SDMASA_R register (0x0 - 0x3).
• ADMA2/ADMA3 selection: ADMA3 is selected by the SDMMC_HOST_CTRL1_R[DMA_SEL] bit field.
• 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 0x1.
• Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register.
• 32-bit Block Count: The SDMMC_SDMASA_R register (0x0 - 0x3) is modified to 32-bit Block Count Register Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, while operating in Host version less than 4 mode (HOST_VER4_ENABLE = 0x0).

0 (Val_0x0): Version 3.00 compatible mode

1 (Val_0x1): Version 4 mode

64-bit Addressing. This bit is effective when the HOST_VER4_ENABLE bit is set to 0x1.

0 (Val_0x0): 32 bits addressing

1 (Val_0x1): 64 bits addressing

Asynchronous Interrupt Enable. This bit can be set if a card supports asynchronous interrupts and this bit is set to 0x1 in the Capabilities registers (SDMMC_CAPABILITIES1_R and SDMMC_CAPABILITIES2_R).

0 (Val_0x0): Disabled

1 (Val_0x1): Enabled

Preset Value Enable. This bit enables automatic selection of SD_CLK frequency and Driver strength in Preset Value registers. When this bit is set, SD_CLK frequency generation (SDMMC_CLK_CTRL_R[CLK_GEN_SELECT], the SDMMC_CLK_CTRL_R[FREQ_SEL]), and the driver strength selection are performed by the Host Controller. These values are selected from set of Preset Value registers based on selected speed mode.

0 (Val_0x0): SD_CLK and driver strength are controlled by Host Driver

1 (Val_0x1): Automatic selection by preset value are enabled